// Copyright (C) 1953-2022 NUDT
// Verilog module name - local_cnt_timing 
// Version: V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         global time synchronization 
//         generate report pulse base on global time
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module local_cnt_timing 
#(
    parameter clk_period = {8'd8,41'h0}//8ns
 ) 
(
        i_clk,
        i_rst_n,
        
		o_local_cnt_rst,
        ov_local_cnt
);
// clk & rst
input                  i_clk;
input                  i_rst_n;

output reg             o_local_cnt_rst;
output       [39:0]    ov_local_cnt;            
reg [64:0]    rv_local_cnt; 
assign ov_local_cnt = rv_local_cnt[64:25];
always @(posedge i_clk or negedge i_rst_n) begin//local time rst 
    if(!i_rst_n)begin
	    o_local_cnt_rst <= 1'b0;
        rv_local_cnt    <= 65'b0;
    end
    else begin
        rv_local_cnt <= rv_local_cnt + clk_period;
		if({1'b0,rv_local_cnt} >= {1'b1,24'h0,41'b0} - {1'b0,16'b0,clk_period})begin
		    o_local_cnt_rst <= 1'b1;
            rv_local_cnt    <= {1'b0,rv_local_cnt} + {1'b0,16'b0,clk_period} - {1'b1,24'h0,41'b0};
		end
		else begin
		    o_local_cnt_rst <= 1'b0;
            rv_local_cnt    <= {1'b0,rv_local_cnt} + {1'b0,16'b0,clk_period};
		end
    end
end
endmodule